I'm planning to order my first custom PCB from JLCPCB, which will only have one RAM chip breakout to include on my breadboard prototype. On my breadboard, I've gotten the following working:
- ICE40 FPGA (Architry Cu)
- ESP32-C3 MCU (RISC-V + Wifi/BT)
- OV7670 Camera (640x480 30 FPS)
I'd like to use the FPGA to read the camera data and store it in a RAM. Also, I'd like the MCU to be able to read single pixels at ~1000 Hz from the RAM. I plan to use the FPGA to manage the interface between the MCU and the RAM as well.
At first, my choice of RAM was a small RAM that is hard to find with a long lead time with JLCPCB. Now, I'm planning to use a slightly larger RAM with shorter lead time. This is the RAM part I'm looking at:
digikey.com/en/products/detail…
The design in the image is the old part. I'm now starting a redesign of the PCB with the new slightly larger RAM.
#foss #fosh #freemanufacturing #bce #bcecoop #bcecoopinc #fpga #mcu #ram #maker #ee #breadboard #prototype #jlcpcb
Bo Morgan
in reply to Bo Morgan • • •Finished a redesign of my first PCB assembly order ever. I'm using JLCPCB and I've ordered the one part in this test design.
This is a 2 layer board to breakout an 8x8 mm DRAM chip with 56 pins so that I can play with it on my breadboard.
#foss #fosh #pcb #pcba #ee #jlcpcb #ram #dram #freemanufacturing #bce #bcecoop #bcecoopinc
Altbot
in reply to Bo Morgan • • •The image depicts a circuit board layout for a BCE Coop Inc. RAM1 module. The board features a central RAM chip surrounded by numerous labeled pins. The pins are organized in two columns, with labels such as "CLK," "A11," "A7," "Vss," "DQ9," "DQ11," "DQ13," "DQ8," "DQ10," "DQ12," "DQ14," "Vss5," "DQ15," "VssQ," "VddQ," "VssQ," "VddQ," "DQ0," "Vdd," "DQ1," "DQ3," "DQ5," "DQ2," "DQ4," "DQ6," "BA0," "A0," "A3," "A2," "Vpp," "A10," "n_CS," "n_WE," "DQ7," "A1," "BA1," "n_RAS," and "DQML." The pins are connected to the RAM chip via red and blue lines, indicating different signal paths. The layout is symmetrical, with the RAM chip at the center, and the pins are labeled in a systematic manner, suggesting a well-organized design.
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